The present invention relates to a semiconductor memory device, particularly to an improvement in a memory cell structure of a dynamic random access the memory (DRAM).
A memory cell of a prior art DRAM comprises one switching transistor and one capacitor, wherein electric charge is transferred into or out of the capacitor through the switching transistor for data storage or data readout. To implement such a structure with a semiconductor device, a planar structure in which a capacitor formed of a silicon substrate, an oxide film, and a polysilicon electrode and a MOS transistor are formed of the same wafer surface. But, with the above-described structure, a limit is approached to the degree of integration
To increase the degree of integration further, a new structure, shown in FIG. 1, is now being studied and developed in which a capacitor C is formed of a cell plate 3 filling a trench 2 provided in a silicon substrate 1, thereby to reduce the area for the capacitor while maintaining the capacitance of the capacitor C. A polysilicon word line 4 serves also as a gate, and an A1 bit line 5 has a contact with one of the main electrodes of the transistor.
Another concept of "gain cell" is also being studied. In this structure each memory cell has an amplification function to compensate for the reduction in the stored electric charge along with the reduction in the size of the elements. An example of this structure is shown in "Extended Abstracts of the 16th (1984) International Conference on Solid State Devices and Materials, Kobe, 1984, pp. 265-268", and is shown in FIGS. 2, 3 and 4. As shown it comprises a bulk sense transistor 11, a polysilicon transistor 12, a writing word line 13, a reading word line 14, a writing bit line 15, a reading bit line 16, and a power supply line 17.
In this gain cell, the electric charge is stored in the capacitors C1 and C2, and the reading of the stored date can be effected by ON/OFF control of the bulk sense transistor 11. There is no inherent limit to the electric charge which can be read out. But with this structure, the transistor 12 connected to one electrode of the charge storage capacitor is a polysilicon transistor having a large leak age current, so that the stored charge may be lost. Another disadvantage is that two word lines and two bit lines are needed.